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Network On Chip
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41	Within the NOC Management Consultancy World Programme No Add to Reading List Source URL: www.grenadaolympic.com Language: English - Date: 2013-01-30 12:09:21 Electronic design automation Network On Chip National Oil Corporation
42	KOSMOS System Design Note 0 Add to Reading List Source URL: www.noao.edu Language: English - Date: 2010-07-30 15:46:06 Electronic engineering Computing National Optical Astronomy Observatory Network On Chip IRAF Kosmos User interface Scripting language Command-line interface User interface techniques Software National Science Foundation
43	194 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 3, NO. 2, MARCH 1992 Virtual-Channel Flow Control William J. Dally, Member, IEEE Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2008-04-03 14:16:32 Network architecture Flow control Network protocols Network On Chip Routing Wormhole switching Throughput Packet switching Channel Computing Computer networking Data transmission
44	A 128 × 128 × 24Gb/s Crossbar Interconnecting 128 tiles in a single hop and Occupying 6% of their area Giorgos Passas, Manolis Katevenis, and Dionisis Pnevmatikatos Inst. of Computer Science (ICS) Foundation for Resear Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2014-02-26 11:59:50 Electronics Crossbar switch Clos network Cell Network On Chip Crossbar Flip-flop Crossbar latch Electronic engineering Electrical engineering Switches
45	Within the NOC Management Consultancy World Programme No Add to Reading List Source URL: www.grenadaolympic.com Language: English - Date: 2013-01-31 16:02:44 Network On Chip Athletics International Olympic Committee Track and field Sports Olympic Games National Oil Corporation
46	Approaching Ideal NoC Latency with Pre-Configured Routes George Michelogiannakis, Dionisios Pnevmatikatos and Manolis Katevenis Institute of Computer Science (ICS) Foundation for Research & Technology - Hellas (FORTH) Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:41 Foundation for Research & Technology – Hellas Network On Chip Latency Electronics Electronic engineering Integrated circuits Routing
47	A 128 x 128 x 24Gb/s Crossbar, Interconnecting 128 tiles in a single hop, and Occupying 6% of their area Giorgos Passas, Manolis Katevenis, Dionisis Pnevmatikatos presentation by Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2014-02-26 11:59:59 Cell Crossbar Electronics Electronic engineering Electronic design automation Network On Chip
48	Design Tradeoffs for Tiled CMP On-Chip Networks ∗ James Balfour , William J. Dally Computer Systems Laboratory Stanford University Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2006-09-12 12:06:57 Computer networking Network performance Throughput Network switch Routing Packet switching Channel Router Asynchronous Transfer Mode Computing Electronic engineering Network architecture
49	A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN. Add to Reading List Source URL: cva.stanford.edu Language: English - Date: 2005-12-01 13:38:04 Routing Flow control Network On Chip Wormhole switching Throughput Network switch Router Traffic flow Channel Network architecture Computing Electronic engineering
50	Low-latency Explicit Communication and Synchronization in Scalable Multi-core Clusters Christoforos Kachris, George Nikiforos, Vassilis Papaefstathiou, Xiaojun Yang, Stamatis Kavadias, Manolis Katevenis Institute of Comp Add to Reading List Source URL: www.ics.forth.gr Language: English - Date: 2013-12-23 07:16:58 Electronic engineering Computer architecture Parallel computing Scratchpad memory CPU cache Remote direct memory access Multi-core processor Network On Chip Throughput Computing Computer memory Computer hardware

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